Qwenputer: RISC-V CPU built inside Qwen3.5
The gist
Developer Divyansh Agrawal released Qwenputer, a modified Qwen3.5-4B with a 32-bit RISC-V CPU compiled into its weights.
The CPU runs inside the model's forward passes, with no external runtime.
How it unfolded
- Oct 28, 2026Agrawal released Qwenputer, a modified Qwen3.5-4B hosting a working 32-bit RISC-V CPU inside its weights, occupying 11 layers in front of Qwen's original 32.
- Oct 28, 2026The processor passed official riscv-tests, its programs matched qemu, and it ran 18 million instructions free-running without a single error; it scored 100% on the NUPA numeracy benchmark versus 48.6% for the base model.
- Oct 29, 2026Multiple outlets reported on the story, describing the CPU executing arithmetic, C and MicroPython within forward passes with no external runtime or tool server.